At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation and SoC Design, we want to meet you.
The Systems Solutions Group (SSG) delivers tool, methodology, architecture, design creation, design verification and physical implementation expertise to enable leading edge customers to complete their most challenging SoC design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Our customers develop SOCs for high-performance computing, automotive, aerospace & defense, and more.
SOC DFT, Principal Engineer Job Description and Requirements We have an immediate opening for a SoC Design-For-Test (DFT) professional at Principal Engineer in Dublin or can be remote Ireland. This is a "hands-on" leadership role that would build, lead, and coordinate the SoC DFT team, including subcontractors in the System Solutions Group (SSG). The role primarily requires development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team.
Responsibilities Lead DFT implementation, integration and verification of System-on-Chip (SoC) and SoC Subsystems from initial specification till tapeout.Lead various aspects of Test architecture including Scan & ATPG, Memory BIST, Logic BIST, Analog/PHY test and post-silicon support.Develop and execute DFT methodologies, strategies, and guidelines to maximize test coverage, reduce test cost, and optimize production yield.Support post-silicon activities, working with test engineering and validation teams as needed.Lead the DFT team, providing technical guidance and mentorship to engineers and manage the team for their professional growth and development.Desirable: DFT experience in Automotive SoCs (or Multi-Die SiPs with 2.5D/3D Packaging) and Functional Safety ISO26262 processes Required Bachelors or Masters degree in Electrical/Electronics/Computer Engineering or equivalentMinimum of 12+ years' experience in SoC/IP/Subsystems DFT domain.Experienced SoC DFT engineers, with experiences in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.Ability to lead a team to perform DFT for complex SoC/IP/Subsystems.Experience with planning and managing DFT activities for SoC/Subsystems/IPs.Strong understanding of design concepts, ASIC flows and stakeholders.Good communication skills.
#J-18808-Ljbffr