Lead Principal Silicon Evaluation Engineer - Cork City, Ireland

Client: Our client, a leading Multinational Semiconductor EDA Software provider, requires a Lead Principal Silicon Evaluation Engineer for a role based in Cork City, Ireland.

Role: You will manage the Silicon Evaluation team as part of a complete SERDES Product Team located in Cork, Ireland.

Responsibilities: Manage the Silicon Evaluation team to validate High Speed SERDES products at data rates up to 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS). Work with other technical domain leads and the program management team to deliver PHY products to the customer on schedule. Ability to hire and attract new team members to build and maintain a complete Silicon Evaluation team. Work with global teams and stakeholders across different time zones (US, EU, India). Education: BEng, MEng, PhD or equivalent. Experience: A minimum of 10 years of silicon validation experience, preferably in the area of SERDES, DDR, or high-speed interface design. Must have at least 4 years of experience managing Silicon Evaluation Engineers as part of a larger mixed signal product team. Strong understanding of lab equipment and measurement techniques for high-speed interfaces (high-speed scopes, probes, spectrum analyzers, BERTs). Must have a thorough understanding of eye diagrams, transmission lines, channel loss, etc., along with associated jitter and signal equalization techniques. Good knowledge of the main board and package design approaches used in the industry. Software proficiency for test scripting, data handling, and reporting using scripting languages such as Python, TCL, etc. Ability to run Verilog test benches and view waves to debug issues. Excellent interpersonal skills and ability to communicate effectively with both technical and non-technical individuals. Excellent problem-solving skills, and ability to work cooperatively in a team environment. Communicate with global teams (US, India, China, EU) which work in different time zones. Lead the Evaluation team to understand requirements, fashion tests, and review results. Mentor junior engineers as required. Additional Skills: Experience with chiplet substrate/package design methodologies and tools. Familiarity with "pre-silicon" verification strategies and tool flows. Interest in publishing academic papers & presenting at conferences (e.g., ISSCC, DesignCon). Contact: For further information, please contact Mícheál at Software Placements on 00353 1 5254642 or email ******.



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