Principal ASIC Design Engineer Cork, Ireland The company is on the lookout for a highly skilled Principal ASIC Design Engineer to join their diverse team.
The ideal candidate will have a strong background in hardware design, ASIC development, and a deep understanding of processor design, on-chip communication, and high-speed interfaces.
As a Principal ASIC Design Engineer, you'll play a pivotal role in developing cutting-edge semiconductor products.
ResponsibilitiesLead the architecture, design, and implementation of complex ASIC designs, including processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.Collaborate with cross-functional teams to define system requirements and specifications for ASIC designs.Utilise proficiency in RTL design techniques, synthesis, timing closure, and verification to ensure successful execution of ASIC projects.Provide mentorship and guidance to junior team members, fostering a culture of continuous learning and development.Drive innovation and optimisation to improve ASIC design methodologies and best practices.QualificationsBachelor's degree in Electrical Engineering, Computer Engineering, or related field.
Master's degree or PhD preferred.Proven experience in ASIC design, with a focus on processor design, on-chip communication, and high-speed interfaces.Expertise in RTL design techniques, synthesis, timing closure, and verification.Strong understanding of semiconductor industry trends and emerging technologies.Excellent communication and collaboration skills, with the ability to work effectively in a diverse and inclusive team environment.Day-to-dayCollaborate with cross-functional teams to define ASIC design requirements and specifications.Lead the architecture and design of complex ASIC designs, utilising expertise in processor design, on-chip communication, and high-speed interfaces.Mentor junior team members, providing guidance and support in ASIC design methodologies and best practices.Stay updated on semiconductor industry trends and emerging technologies to drive innovation and optimisation in ASIC design.