Our client is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Their customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. They hire and develop leaders and innovators who want to make an impact on the world of technology.
This is a technically rewarding role with high visibility within the organization. The team is responsible for supporting customers of CSG subsystems. The group will also implement reference designs on emulation systems and support applications for product demonstrations.
This role requires extensive experience in IP integration and implementing SoC and compute-based systems. You will work closely with compute and interface IP development engineering and build designs to demonstrate the capabilities of CSG subsystems and components.
Responsibilities: Develop, implement, and debug SoC reference systems.Integrate compute, memory and interface IP in system designs.Analyse IP products and implementation flows.Identify gaps and work with development teams to improve products.Develop collateral, and training material for CSG system customers.Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.Stay up to date with latest industry trends, technologies, and design methodologies, and incorporate them into team's workflows.Requirements: BS in Electronic Engineering/Computer Science with 8+ years work experience, or MS in EE/CS with 4+ years' experience.Must have at least 3 years of experience in ASIC design, integration, or verification.Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.Expertise in Verilog/System Verilog for coding and verification.Proficiency in RTL design techniques, including synthesis, timing closure, and verification.Experience in using UVM for functional verification of ASIC designs.Experience with EDA tools like Cadence and Synopsys for design simulation and verification.Extensive experience with FPGA emulation, design tools, and verification.
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