Client:
Our client, a leading Multinational Semiconductor Telecom Company, requires Staff or Senior ASIC Design Verification Engineers with Sensors for roles based in Cork City, Ireland.
The position is technology-focused and involves participation in a broad range of sensors systems engineering activities within the Sensors Technologies group. Role: You will be deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification, developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments, and verifying sensor algorithms RTL for ASIC tapeout quality delivery.
Responsibilities:Test plan development based on Design documents and interaction with design/systems engineersImplementing C model integration within UVM framework.Writing SystemVerilog assertionsDebugging, verifying, optimizing, and bit-exact matching with test vectorsAnalyzing coverage data and working with Design teams to address coverage holesDeveloping/augmenting framework for running regressionsDebugging regression failures with design/Systems teamsSupport integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration levelPython automation for improving workflows and team efficiencyParticipate in all project reviewsSupporting software and other teams with debugDocumentationEducation:Bachelor's degree in Science, Engineering, or related field. Experience:3+ years ASIC design verification, UVM-based functional verification, or related work experience.Experience using formal verification tools like Jasper or VC_Formal is a plusExperience with SystemC and Matlab are a plus.Gate level Simulation debug and usage of power extraction tools is a plusExperienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodologyExperienced with Assertions like System Verilog AssertionsExperience with debugging test failures and reporting verification results to achieve the expected code/functional/line coverage goalsExtensive usage of RTL simulation tools.UVM, System Verilog, Perl/Python shell-scripting skills requiredFamiliarity with C/C++Strong analytical skills and ability to work in a dynamic and fast-paced team environmentExcellent written and verbal skillsStrong interpersonal skills and a good team playerWorking Model: The company offers a hybrid working model of 3 days onsite and 2 days from home. Well-being and life balance are fundamental. As such, company policy allows employees to blend short-term remote working with annual leave. Contact:
For further information, please contact Mícheál at Software Placements on 00353 1 5254642 or email ******.
#J-18808-Ljbffr
