Lead Digital Design Engineer (Ethernet) Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality.
Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial, and health.
Job Title: Lead Design Engineer (Ethernet)
Location: Cork
Reports to: Design Engineering Director
Job Overview:
The Cadence Silicon Solutions Group (SSG) develops leading-edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and reduce time to volume.
The Lead Design Engineer will be based in Cork, as part of an experienced Ethernet Controller IP Development Team and will work with long-established Controller development sites in Europe, the US, and India.
Job Responsibilities:
Design solutions for the latest Ethernet controller features and customer requirements. Understand and Interpret IEEE 802.3 specifications. Follow a top-down and bottom-up design methodology to partition the design. Design RTL in a highly configurable and automated environment. Work across disciplines including Design, Verification, Customer Support & Delivery. Utilize Cadence's Design Automation flow and IP development tools. Perform synthesis, timing closure, reviewing, and defining SDC constraints. Collaborate with Team to develop plans and schedules. Participate in design reviews and drive technical correctness. Job Qualifications:
Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline. 3-7 years' experience in the microelectronics/EDA industry. Experience in Ethernet Systems & Packet Protocols. Experience in Ethernet Hardware design, debug, and verification. Experience in Verilog RTL Design. Experience in C, C++, Python, or Java. Experience of Metric Driven Verification (MDV) or other Verification Methodology. Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential. Excellent oral and written English essential. Self-motivated with excellent planning, interpersonal, and communication skills. Additional Skills/Preferences:
Experience of AMBA protocols such as CHI, AXI, AHB & APB. Experience with Serial interfaces such as UARTs, SPI, Jtag. Experience with SOC applications and DFT. Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred. Additional Information:
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
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