Client:
Our client, a leading Multinational Semiconductor Organisation, requires a Principal Analog Design Engineer (Memory/Audio Interface) for a role based in Cork City, Ireland.
You will design high-speed memory interface analog components used in state-of-the-art DDR memory interface PHYs in leading-edge technology nodes. This includes blocks such as IOs, amplifiers, comparators, drivers, duty cycle correctors, PLLs, DLLs, level shifters, etc. in advanced IC nodes in volume production.
Role: As Principal Design Engineer, you will provide technical direction and coordination to the analog IC design team, identify opportunities to advance technology in analog design, and participate in strategic internal analog IP development.
Responsibilities: Design of High-Speed memory interface products at data rates up to and exceeding 36 Gbps on leading-edge technology nodes (e.g. 5nm FinFET CMOS).Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections.Collaborate with Technical Team Leads in the areas of circuit design and architecture.Mentor Junior Design Engineers when project needs arise.Work with global teams (US, India, China, EU) across different time zones.Education: Successful candidate should have a BEng, MEng qualification or an equivalent qualification.Experience: Minimum of 4 years of CMOS design experience, preferably in the area of CMOS SERDES, DDR or high-speed I/O IC design.Good understanding of jitter and signal equalization techniques.Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High-Speed Clock Distribution, Bias and Bandgap, Voltage Regulators.Excellent problem-solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment.Proficiency in using CAD tools for circuit simulation, layout, and physical verification is required.Cadence tool experience and design experience in Lab test experience as part of silicon evaluation is advantageous.Contact:
For further information, please contact Mícheál at Software Placements on 00353 1 5254642 or email ******.
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